1. Field of the Invention
This invention relates generally to integrated circuits and more particularly concerns the use of scan-flops in integrated circuits to maximize fault coverage during testing procedures, without sacrificing chip speed.
2. Description of the Related Art
In an effort to remain competitive in the marketplace, chip manufacturers are constantly striving to optimize the design and efficiency of their integrated circuits (ICs) by increasing both chip speed and the density of internal circuit components. Commensurate with meeting these objectives is a concerted effort on the part of chip manufacturers to maximize fault coverage when testing their IC designs. Presently, a 95% fault coverage is common, with this percentage expected to increase to at least 97% fault coverage in the near future. Ideally, of course, chip manufacturers strive for 100% fault coverage.
Testing of ICs during production has become more difficult and expensive due to the limited access from the I/O pins to the chip's logic core and the limited time available for each IC to be on a tester. A full-scan method has become an industry standard to increase fault coverage while decreasing test time during production. The full-scan approach generally involves the incorporation of scan-flops fabricated into an IC chip throughout its logic core. A scan-flop, sometimes referred to as a scan-flop cell, is essentially a flip-flop with the addition of a multiplexer that permits the IC to operate in both a test mode and a functional mode. As such, full-scanning of a chip's logic core involves replacing-each flip-flop with a scan-flop. However, while the utilization of scan-flops facilitates testing the integrity of the logic core, the additional logic and routing inherent in existing scan-flops necessarily increases the propagation delay through their associated flip-flops, thereby-reducing the functional speed of the IC.
This propagation delay is attributed to two factors that include scan muxing (i.e., multiplexing) and scan routing. Scan muxing delay can be reduced by optimizing the design of a scan-flop's multiplexer, while scan routing delay is generally avoided utilizing the scan-flop's inverted output (NQ) provided it is not being used. It is typical, however, for most IC designs to rely upon the scan-flop's inverted output NQ during functional operations, thereby resulting in increased scan routing delay.
With initial reference to FIGS. 1(a) and 1(b), the incorporation of existing scan-flop designs into an IC, for the purpose of testing the logic core may now be better appreciated, as well as the drawbacks associated therewith. In FIG. 1(a) an integrated circuit chip 10 is schematically shown to have a plurality of input pins 14 and output pins 16. Within chip 10 is the logic core consisting of various logic chains, such as logic chains 18 and 20. Each logic chain includes a plurality of scan-flops and their associated logic arrays. For example, logic chain 18 includes scan-flops 21-23 and their associated logic arrays 24 and 25, while logic chain 20 includes scan-flops 26-28 and their associated logic arrays 29 and 30. Of course, it should be readily appreciated that FIG. 1(a) is a somewhat simplified representation of a typical IC chip 10 in that existing designs would necessarily include many more such logic chains and more associated circuitry components.
Chip 10 is operative in both a test mode and a functional mode. When operating in the test mode, it is desirable to test the integrity of the chip's various logic arrays in a time efficient manner and with a high fault coverage, as discussed above, so that chip 10 exhibits reliable performance characteristics when in the functional mode. To this end, and as known in the art, the testing procedure involves the use of an automatic test pattern generation (ATPG) simulation to inject a test vector into the chip to ascertain whether there are any problems within the particular logic arrays residing between the scan-flops. More specifically, the ATPG creates the test vectors which are simultaneously presented to input pins 14 of chip 10. The test vectors are initially loaded into the scan-flops of the respective logic chains in such a manner that the internal logic arrays within the chains are bypassed.
This testing procedure may best be appreciated with reference now to FIG. 1(b) of the prior art which, for representative purposes, shows only a portion of logic chain 18 in FIG. 1(a). Here it may be seen that logic array 24 is interposed in electrical communication between scan-flops 21 and 22. Scan-flop 21 includes a multiplexer 32 and a synchronous flip-flop 34. Likewise, scan-flop 22 includes a multiplexer 42 and a synchronous flip-flop 44. Flip-flops 34 and 44 may be positive-edge triggered D flip-flops, as shown. When selected for test mode operation, the test vector is injected into logic chain 18 at input pin 14 upon the transition of a clocked enable signal on line 50 from a logic "low" to a logic "high". The test vector proceeds along a scan path that bypasses logic array 24 and is sequentially stored into each of the scan-flops, including scan-flops 21 and 22. That is, the test vector is initially transmitted to the serial input SI of scan-flop 21 and proceeds through multiplexer 32 for storage into flip-flop 34. From here, the test vector is transmitted along communication line 52 from the inverted output NQ of flip-flop 34 to the serial input SI of flip-flop 22, thereby bypassing logic array 24. The test vector then passes through the second scan-flop's multiplexer 42 for storage into flip-flop 44. The test vector is sequentially stored in the remaining scan-flops of logic chain 18 in a similar manner.
Once the test vector has been initially loaded into the scan-flops of logic chain 18, chip 10 is selected for functional mode operation to pass the test vector into each of the logic arrays. For example, the test vector stored in flip-flop 34 of scan-flop 21 is passed into logic array 24 along either or both of the flip-flop's Q output line 54 or NQ output line 56. Logic array 24 processes the information and transmits its results along data line 58 to second scan-flop 22, and so on down the logic chain. Chip 10 is then returned to its test mode and generates an output test vector for logic chain 18 at output pin 16 shown in FIG. 1(a). The input test vector and the output test vector are then compared by the ATPG to ascertain if there are any discrepancies, indicating a fault within one of the logic arrays that forms part of logic chain 18.
While the full-scan approach discussed above is widely used, it does have inherent drawbacks. One of these drawbacks is that undesirable propagation delay occurs in communication line 52 of the scan path, i.e. the one that bypasses logic array 24 during initial loading of the test vector. In sub-micron technology, wiring capacitance of communication line 52 is generally more significant than the input capacitance of logic array 24. Because communication line 52 is relatively long in that it bypasses logic array 24, its wiring capacitance can double the load seen by inverted output NQ of flip-flop 34. This not only results in lost speed during the testing of logic chain 18, but also detrimentally impacts chip speed during functional mode operation because the inverted output NQ of each of the flip-flops sees an increased load at all times.
Another inherent drawback of the full-scan approach discussed above is due to the necessary incorporation of a multiplexer within each of the scan-flops to permit test mode operation. The mere existence of these multiplexers, and the internal transistors associated with them, also causes additional propagation delay during test mode and functional mode operation of the chip.
In view of the foregoing, what is needed is a new and improved scan-flop design for use in an integrated circuit to increase testing efficiency of the circuit's core logic by reducing test time without jeopardizing test results. It would also be desirable for such a scan-flop to reduce propagation delay during functional mode operation of the integrated circuit. The present invention is directed to meeting these needs, among others.